TMDXEVM5515【PDF 83/159 页】EVAL MODULE DSP FOR C55XX

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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013

5.7

5.7.1

Reset

The device has two main types of reset: hardware reset and software reset.

Hardware reset is responsible for initializing all key states of the device. It occurs whenever the RESET

pin is asserted or when the internal power-on-reset (POR) circuit deasserts an internal signal called

POWERGOOD. The device's internal POR is a voltage comparator that monitors the DSP_LDOO pin

voltage and generates the internal POWERGOOD signal when the DSP_LDO is enabled externally by the

DSP_LDO_EN pin. POWERGOOD is asserted when the DSP_LDOO voltage is above a minimum

threshold voltage provided by the bandgap. When the DSP_LDO is disabled (DSP_LDO_EN is high), the

internal voltage comparator becomes inactive, and the POWERGOOD signal logic level is immediately set

high. The RESET pin and the POWERGOOD signal are internally combined with a logical AND gate to

produce an (active low) hardware reset (see Figure 5-11 , Power-On Reset Timing Requirements and

Figure 5-12 , Reset Timing Requirements ).

There are two types of software reset: the CPU's software reset instruction and the software control of the

peripheral reset signals. For more information on the CPU's software reset instruction, see the

TMS320C55x CPU 3.0 CPU Reference Guide (literature number: SWPU073 ). In all the device

documentation, all references to "reset" refer to hardware reset. Any references to software reset will

explicitly state software reset.

The device RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC

core. This POR monitors the voltage of CV DDRTC and resets the RTC registers when power is first applied

to the RTC core.

Power-On Reset (POR) Circuits

The device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another for the

rest of the chip (MAIN POR).

5.7.1.1

RTC Power-On Reset (POR)

The RTC POR ensures that the flip-flops in the CV DDRTC power domain have an initial state upon

powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC

time registers need to be initialized with the current time and date when power is first applied.

5.7.1.2

Main Power-On Reset (POR)

The device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until specific

voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the

DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until the following conditions

are satisfied:

?

?

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LDOI is powered and the bandgap is active for at least approximately 8 ms

VDD_ANA is powered for at least approximately 4 ms

DSP_LDOO is above a threshold of approximately 950 mV (see Note: )

Note: The POR comparator has hysteresis, so the threshold voltage becomes approximately 850 mV after

POWERGOOD signal is set high.

Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal

is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's

global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global

reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence,

see Section 3.4 , Boot Sequence .

When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is

de-activated and the POWERGOOD signal is immediately set high. The RESET pin will be the sole

source of hardware reset.

Copyright ? 2010–2013, Texas Instruments Incorporated

Peripheral Information and Electrical Specifications

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